1. Field of the Invention
The invention relates to semiconductor chips, and more particularly to a method and system which traces on a same network are shorted to improve chip yield and performance.
2. Background Description
Chip designers have long attempted to improve chip yield and reliability while simultaneously reducing wiring resistance and wiring opens by including one or more redundant vias in the chip design. However, adding redundant vias does not satisfactorily solve the aforementioned problems because adding extra vias increases path length and wiring resistance, which reduces the chip's overall yield. Using vias to connect devices on a semiconductor chip cause other problems. For example, the capacitance inherent in vias can change the characteristic impedance of a trace. Additionally, if vias are positioned close to metal traces or other devices, device-electromagnetic-circuit coupling may result. Such coupling may adversely affect the performance of a neighboring MOSFET.
Various types of layered substrates may be used to form integrated circuits. For example, a two layer substrate may include two metal (signal) traces separated by an organic or ceramic dielectric. Traces on the top layer can be connected to traces on the bottom layer using vias, which may be drilled. As another example, a built-up substrate consisting of three or more layers may be constructed by building it up, one layer at a time. Illustratively, a four-layer substrate is similar to the two-layer substrate, except that the four-layer substrate includes two additional layers, usually ground and power planes, which are sandwiched between the top and bottom layers. In such a substrate, vias are typically laser-cut to a significantly smaller diameter than the drilled vias commonly used in two-layer substrates.
A significant disadvantage to using vias is that such use creates lengthy electrical paths. FIG. 1 illustrates one such conventional electrical path. As shown, the electrical path begins with metal trace 107 and flows through via 111 to the metal trace 115 positioned on the next layer. From metal trace 115, the electrical path flows through a second via 113, which completes the path by connecting to the metal trace 109, which is formed on the same layer of the substrate as metal trace 107. Such a long electrical path is practical where metal traces (or devices) on different layers need to be connected with each other. However, in cases where two traces on the same network are positioned adjacent each other on the same substrate layer, using vias to connect one of the adjacent traces to the other creates an unnecessarily long electrical path. The long electrical path not only occupies a chip's volume, but also increases resistance, which decreases chip yield. A solution is needed that reduces or eliminates the number of redundant vias and decreases wiring resistance, while also improving overall chip yield and reliability. Accordingly, a solution is needed that decreases wiring resistance, rendering associated non-redundant vias unnecessary, and thus reduces or eliminates the number of redundant vias needed, while also improving overall chip yield and reliability.